8562 VIC-II (NTSC)¶

Video Interface Controller

MOS 6567 (NTSC), NMOS, 1982
MOS 8562 (NTSC), HMOS-II

MOS 6569 (PAL), NMOS, 1982
MOS 8565 (PAL), HMOS-II

PCB ASSY NO. usage:

Pinout¶

            +-----\/-----+
      DB6 <>|01        40|-- Vcc
      DB5 <>|02        39|<> DB07
      DB4 <>|03        38|<> DB08
      DB3 <>|04        37|<> DB09
      DB2 <>|05        36|<> DB10
      DB1 <>|06        35|<> DB11
      DB0 <>|07        34|<> A10
    IRQ_l <<|08        33|<> A09
    LP IN ->|09        32|<> A08
     CS_l ->|10        31|<> A07
      R/W <>|11        30|<> A06 ('1')
       BA <-|12        29|<> A05 (A13)
      Vdd --|13        28|<> A04 (A12)
Color out <-|14        27|<> A03 (A11)
 Sync/Lum <-|15        26|<> A02 (A10)
      AEC <-|16        25|<> A01 (A09)
       Φ0 <-|17        24|<> A00 (A08)
    RAS_l <-|18        23|<> A11
    CAS_l <-|19        22|<- ΦIN Video Clock In
      Vss --|20        21|<- ΦCL Color Clock In
            +------------+

Multiplexed addresses in parenthesis

Signal Description¶

Pin(s)	Signal	Direction	Description
1-7	D6-D0	in/out	Data bus.
8	IRQ_l	out	Interrupt ReQuest. This pin is active LOW: it goes LOW when an interrupt was toggled in the VIC-II. There are four possible sources for an IRQ: rasterline lightpen sprite-sprite collision sprite-background collision
9	LP	in	LightPen. A falling edge on this input causes an interrupt.
10	CS_l	in	Chip Select. Is brought LOW to enable access to the circuit registers in conjunction with the address and RW pins. CS_l LOW is recognized only while AEC and Phase 0 are HIGH.
11	R/W_l	in	Read/Write_l. LOW=write to registers, HIGH = read from registers.
12	BA	out	BusAvailable. The BA line is normally HIGH but is brought LOW during Phase 1 to indicate that the VIC chip will require a Phase 2 data access. Three Phase 2 times are allowed after BA LOW for the processor to complete any current memory accesses. On the fourth Phase 2 after BA LOW, the AEC signal will remain LOW during Phase 2 as the VIC fetches data.
13	Vdd	N/A	Vdd, reference voltage. Connected to +12V DC (NMOS-Chips 6567, 6569) min 11.4V max 12.6V or +5V DC (HMOS-II 8562, 8565). min 4.75V? max 5.25V?
14	COLOR	out	COLOR output. Contains all the chrominance information, including the color reference burst and the color of all display data.
15	SYNC/LUM	out	SYNC/LUMimance output. Contains all the video data, including horizontal and vertical syncs, as well as the luminance information of the video display.
16	AEC	out	Address Enable Control. Directly connected with AEC of the CPU. When going LOW, the CPU puts its bus lines into HIGH impedance state and is thus totally decoupled from the rest of the system, so that the VIC-II can take control over it.
17	Φ 0	out	Phi 0. The VIC-II outputs the system clock for the 6510 by Pin Φ IN / 8.
18	RAS_l	out	Row Address Strobe.
19	CAS_l	out	Column Address Strobe.
20	Vss	N/A	Vss, 0V (GND).
21	Φ COLOR	in	Phi color. The color clock for the VIC-II. 14.31818 MHz for NTSC, 17.734472MHz for PAL.
22	Φ IN	in	Phi in. DOT CLOCK for the VIC-II. 8.18 MHz for NTSC, 7.88 MHz for PAL.
23	A11	in/out	Bit 11 of video Address bus.
24-29	A0/A8-A5/A13	in/out	Multiplexed video Address bus.
30-34	A6-A10	in/out	Bits 6-10 of video Address bus.
35-38	D11-D8	in/out	Color RAM data bus.
39	D7	in/out	Bit 7 of Data bus.
40	Vcc	N/A	Supply voltage +5V DC min 4.75V max 5.25V.