6526 CIA¶
Complex Interface Apapter
Pinout¶
+-----\/-----+
Vss --|01 40|<> CNT
PA0 <>|02 39|<> SP
PA1 <>|03 38|<- RS0
PA2 <>|04 37|<- RS1
PA3 <>|05 36|<- RS2
PA4 <>|06 35|<- RS3
PA5 <>|07 34|<- RES_l
PA6 <>|08 33|<> DB0
PA7 <>|09 32|<> DB1
PB0 <>|10 31|<> DB2
PB1 <>|11 30|<> DB3
PB2 <>|12 29|<> DB4
PB3 <>|13 28|<> DB5
PB4 <>|14 27|<> DB6
PB5 <>|15 26|<> DB7
PB6 <>|16 25|<- Φ2 IN
PB7 <>|17 24|<- FLAG_l
PC_l <-|18 23|<- CS_l
TOD ->|19 22|<- R/W_l
Vcc --|20 21|>> IRQ_l
+------------+
Signal Description¶
Pin(s) |
Signal |
Direction |
Description |
|---|---|---|---|
1 |
Vss |
N/A |
Vss, 0V (GND) |
2-9 |
PA0-PA7 |
in |
Port A |
10-17 |
PB0-PB7 |
in |
Port B |
18 |
PC_l |
out |
Port Control Handshaking. PC_l will go low for one cycle following a read or write of PORT B. This signal can be used to indicate “data ready” at PORT B or “data accepted” from PORT B. Handshaking on 16-bit data transfers (using both PORT A and PORT B) is possible but always reading or writing PORT A first. |
19 |
TOD |
N/A |
Time Of Day. The TOD clock is a special purpose timer for real-time applications. TOD consists of a 24-hour (AM/PM) clock with 1/10th second resolution. It is organized into 4 registers: 10ths of seconds, Seconds, Minutes and Hours. The AM/PM flag is in the MSB of the Hours register for easy bit testing. Each register reads out in BCD format to simplify conversion for driving displays, etc. |
20 |
Vcc |
N/A |
Vcc +5 V |
21 |
IRQ_l |
out |
The Interrupt ReQuest Output is an open drain output normally connected to the processor interrupt input. An external pullup resistor holds the signal high, allowing multiple IRQ_l outputs to be connected together. The IRQ_l output is normally off (high impedance) and is activated low as indicated in the functional description. |
22 |
R/W_l |
in |
The Read/Write Input signal is normally supplied by the CPU and controls the direction of data & transfers of the 6526. A high on R/W_l indicates a read (data transfer out of the 6526), while a low indicates a write (data transfer into the 6526). |
23 |
CS_l |
in |
The Chip Select Input controls the activity of the 6526. A low level on CS_l while phi2 is high causes the device to respond to signals on the R/W and address (RSx) lines. A high on CS_l prevents these lines from controlling the 6526. The CS_l line is normally activated (low) at phi2 by the appropriate address combination. |
24 |
FLAG_l |
in |
FLAG_l is negative edge sensitive input which can be used for receiving the PC_l output from another 6526, or as a general purpose interrupt input. Any negative transition on FLAG_l will set the FLAG_l interrupt bit. |
25 |
Φ2 |
in |
The phi2 clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system bus. |
26-33 |
DB7-0 |
in/out |
The eight Data Bus Input/Output pins transfer information between the 6526 and the system data bus. These pins are high impedance inputs unless CS_l is low and R/W_l and phi2 are high to read the device. During this read, the data bus output buffers are enabled, driving the data from the selected register onto the system data bus. |
34 |
RES_l |
in |
RESet Input. A low on the RES_l pin resets all internal registers. The port pins are set as inputs and port registers to zero (although a read of the ports will return all high because of passive pullups). The timer control registers are set to zero and the timer latches to all ones. All other registers are reset to zero. |
35-38 |
RS3-0 |
in |
The Address Inputs select the internal register as described by the Register Map. |
39 |
SP |
in/out |
Serial Port (SDR). The serial port is a buffered, 8-bit synchronous shift register system. A control bit selects input or output mode. |
40 |
CNT |
in/out |
CouNT |
